Workshop 17: Instruction-Level Parallelism
Programme Committee:
Chris Jesshope,
Massey University, New Zealand, Global Chair
Damal K.Arvind,
University of Edinburgh, UK, Local Chair
Kemal Ebcioglu, IBM Watson, USA, Vice-Chair
Michael Schlansker, Hewlett-Packard, USA, Vice-Chair
Michael Smith,
Harvard University, USA, Vice-Chair
Description:
Instruction-level parallelism (ILP) is now the norm in modern
microprocessor devices using one or more of the following techniques:
superscalar, superpipelining, VLIW and multi-threading. The goal of
course is to increase the throughput of a computational device by
issuing more than a single instruction in a single clock period. There
are many implications from these developments in microprocessor
architecture ranging from pure design optimisations to compilation
techniques. Indeed, many of these issues are interdependent and cannot
be considered in isolation. This workshop is intended to present a
forum for researchers and developers in this field to discuss and
debate key issues of common interest.
Topics of interest include:
- memory hierarchy and latency
- performance analysis
- asynchronous architectures for ILP
- compilation and optimisation
- speculation vs. threading
- dynamic vs. static scheduling
(C)opyright
by University of Passau,
Sven Anders
14.05.1997