Workshops 10 + 11 + 14
Workshop 10: Image and Signal Processing and Special-Purpose Processors
Programme Committee:
Patrice Quinton, IRISA-CNRS, Rennes, France, Global Chair
Hartmut Schmeck,
University of Karlsruhe, Germany, Local Chair
Ed F. Deprettere,
Delft University of Technology, The Netherlands, Vice-Chair
Edward A. Lee,
UC Berkeley, USA, Vice-Chair
Description:
Our evolving information society increasingly relies on
efficient algorithms and architectures for Signal and Image Processing
(SIP). Due to its extremely high performance requirements, SIP has
always been one of the major application areas and one of the driving
forces behind the design of special-purpose processors. New challenges
arise from areas like computer vision or multi-media applications.
Submissions are invited from academia and industry on various aspects
of SIP: parallel architectures, methods for designing parallel
algorithms, languages and environments for programming parallel
architectures or for designing special-purpose architectures for SIP
applications, applications of parallel processing in SIP, interactions
between algorithms, architectures and their development and design
methodologies.
Topics of interest include:
- parallel architectures and algorithms
- dynamically reconfigurable architectures
- parallel DSP systems
- application specific parallel architectures
- parallel custom computing machines for SIP
- methods and tools for the design of SIP architecture
- SIP design environments
- computer vision
- parallel video servers
- signal and image compression
- dependability and security of SIP
Workshop 11: Design Automation of Parallel VLSI Circuits
Programme Committee:
Lothar Thiele,
ETH Zurich, Switzerland, Global Chair
Peter
Marwedel, University of Dortmund, Germany, Local Chair
Nikil Dutt,
UC Irvine, USA, Vice-Chair
Patrice Quinton, IRISA-CNRS, Rennes, France, Vice-Chair
Description:
A major emphasis in design automation of electronic
systems is currently on the design of complex domain- or
application-specific systems, such as wireless communication,
multimedia processing, computer networking, telecommunication and
automotive electronics systems. Such systems are directly connected to
their physical environment and are therefore called embedded systems.
Due to the high demands on the processing power in these
application areas, parallelism must be exploited to meet the real-time
requirements. Design automation has to provide techniques for mapping
specifications onto systems which, in general, will be comprised of a
major number of processors and special hardware components working in
parallel. The focus of this workshop is on design automation
techniques directed at the exploitation of concurrency. In particular,
this includes scheduling techniques for mapping a single application
onto multi-processor architectures, hardware/software interface
synthesis, techniques for exploiting homogeneous processor arrays and
other techniques indicated in the list of keywords below.
Topics of interest include:
- application-specific parallel architectures:
- design automation for parallel custom computing on FPGAs, systolic arrays,
- aspects of parallelism in retargetable code generation, application-specific
instruction sets,
- mapping algorithms onto parallel VLSI architectures
- design automation for parallel heterogeneous VLSI systems:
- specification and models of computation, scheduling and communication synthesis,
- exploitation of concurrency in hardware-software co-design, storage
and power optimization
Workshop 14: Parallel Computer Architecture
Programme Committee:
Per Stenström, Chalmers
University, Sweden, Global Chair
Karl Dieter Reinartz, University of Erlangen, Germany, Local Chair
André Seznec, IRISA, Rennes, France, Vice-Chair
David Snelling,
University of Manchester, UK, Vice-Chair
Description:
Parallel computer architecture is concerned with how future computer
systems should be designed to meet the performance demands of emerging
applications through parallelism. While microprocessors today exploit
instruction-level parallelism, parallel computer architecture is
mainly concerned with how we use microprocessors as building blocks to
exploit coarser grain parallelism at the thread level. Important
architectural issues are how to design parallel computer systems that
allow for efficient coordination and communication inside the system
as well as with the outside world through efficient (parallel) I/O
systems.
The scope of this workshop will include (but is not limited to)
parallel computer architectures (general-purpose as well as
special-purpose), the impact of emerging microprocessor architectures
on parallel computer architectures, innovative memory designs to hide
and reduce the access latency, multi-threading, and parallel I/O
systems. Papers will be expected to cover architectural ideas,
analysis and modelling, or practical implementations and their
relation to the demands by current and emerging application domains.
Topics of interest include:
- parallel architectures
- caches
- multi-threading
- innovative memories
- parallel I/O
- latency tolerance
(C)opyright
by University of Passau,
Sven Anders
14.05.1997